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| MM74C165 Parallel-Load 8-Bit Shift Register October 1987 Revised May 2002 MM74C165 Parallel-Load 8-Bit Shift Register General Description The MM74C165 functions as an 8-bit parallel-load, serial shift register. Data is loaded into the register independent of the state of the clock(s) when PARALLEL LOAD (PL) is low. Shifting is inhibited as long as PL is low. Data is sequentially shifted from complementary outputs, Q7 and Q7, highest-order bit (P7) first. New serial data may be entered via the SERIAL DATA (Ds) input. Serial shifting occurs on the rising edge of CLOCK1 or CLOCK2. Clock inputs may be used separately or together for combined clocking from independent sources. Either clock input may be used also as an active-low clock enable. To prevent double-clocking when a clock input is used as an enable, the enable must be changed to a high level (disabled) only while the clock is HIGH. Features s Wide supply voltage range: 3V to 15V s Guaranteed noise margin: 1V s High noise immunity: 0.45 VCC (typ.) s Low power TTL compatibility: fan out of 2 driving 74L s Parallel loading independent of clock s Dual clock inputs s Fully static operation Ordering Code: Order Number MM74165N Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Top View (c) 2002 Fairchild Semiconductor Corporation DS005897 www.fairchildsemi.com MM74C165 Block Diagrams *Please look into Section 8, Appendix D for availability of various package types. Truth Table State PL Clock1 Inputs Clock2 (as enable) Parallel Load Enable Shift (with Ds) Shift (with Ds) Hold (Disable) L H H H H X L X L L L H X X H L X P0...P7 X X X X P0 P0 H L L P1 P1 P0 H H P7 P7 P6 P5 P5 P7 P7 P6 P5 P5 Ds P0 thru P7 Internal Q0 Q1 Outputs Q7 Q7 X = Don't Care H = VIN(1) L = VIN(0) = Clock transition from VIN(0) to VIN(1) P0 thru P7 = Data present (and loaded into) parallel inputs Q0 thru Q6 = Internal flip-flop outputs www.fairchildsemi.com 2 MM74C165 Absolute Maximum Ratings(Note 1) Voltage at Any Pin Operating Temperature Range Storage Temperature Range Absolute Maximum VCC Power Dissipation Dual-In-Line Small Outline Operating VCC Range Lead Temperature (Soldering, 10 seconds) 260C 700 mW 500 mW 3V to 15V Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. -0.3V to VCC + 0.3V -55C to +125C -65C to +150C 18V DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) ISOURCE ISOURCE ISINK ISINK Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Logical "1" Input Current Logical "0" Input Current Supply Current Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V, IO = -10 A VCC = 10V, IO = -10 A VCC = 5V, IO = +10 A VCC = 10V, IO = +10 A VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V VCC = 4.75V VCC = 4.75V VCC = 4.75V, IO = -360 A VCC = 4.75V, IO = 360 A VCC = 5V TA = 25C, VOUT = 0V VCC = 10V TA = 25C, VOUT = 0V VCC = 5V TA = 25C, VOUT = V CC VCC = 10V TA = 25C, VOUT = V CC 2.4 0.4 VCC - 1.5 0.8 -1.0 0.005 -0.005 0.05 300 4.5 9.0 0.5 1.0 1.0 3.5 8.0 1.5 2.0 V V V V A A A V V V V Min Typ Max Units CMOS TO LPTTL INTERFACE OUTPUT DRIVE (See Family Characteristics Data Sheet) (short circuit current) -1.75 -8.0 1.75 8.0 -3.3 -15 3.6 16 mA mA mA mA 3 www.fairchildsemi.com MM74C165 AC Electrical Characteristics TA = 25C, CL = 50 pF, unless otherwise noted Symbol tpd0, tpd1 tpd0, tpd1 tS tS tH tS tH tW tW fMAX tr, tf CIN CPD Parameter (Note 2) Conditions Min Typ 200 80 200 80 150 60 50 30 50 30 150 60 50 30 75 30 25 15 0 0 75 30 0 0 70 30 85 30 2.5 5 10 5 5 65 6 12 200 100 180 90 Max 400 200 400 200 Units ns ns ns ns ns ns ns ns ns MHz s pF pF Propagation Delay Time to a Logical "0" or VCC = 5V Logical "1" from Clock or Load to Q or Q Logical "1" from H to Q or Q Clock Inhibit Set-up Time Serial Input Set-up Time Serial Input Hold Time Parallel Input Set-Up Time Parallel Input Hold Time Minimum Clock Pulse Width Minimum Load Pulse Width Maximum Clock Frequency Maximum Clock Rise and Fall Time Input Capacitance Power Dissipation Capacitance VCC = 10V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V (Note 3) (Note 4) Propagation Delay Time to a Logical "0" or VCC = 5V Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note AN-90. Switching Time Waveform Note A: The remaining six data and the serial input are LOW. Note B: Prior to test, HIGH level data is loaded into the P7 input. www.fairchildsemi.com 4 MM74C165 Logic Waveform 5 www.fairchildsemi.com MM74C165 Parallel-Load 8-Bit Shift Register Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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